Keynotes

ABSTRACT: 

Quantum computing is moving from promise to practice. That shift doesn’t just raise hardware questions—it creates an urgent need for design and diagnostics expertise. Like classical software, quantum programs must be specified, optimized, and compiled. But unlike classical software, every step happens under harsher constraints: no cloning of intermediate states, measurement that destroys information, device noise and limited connectivity that distort intent, and small changes that can have outsized effects.

This talk offers an accessible introduction to quantum computing and then illustrates representative design and diagnostic tasks: realizing applications into quantum workflows, compiling them to survive today’s hardware limits, and debugging quantum programs—despite the inability to inspect internal states, the statistical nature of errors, and the absence of familiar breakpoints. Finally, we take a brief look ahead to fault‑tolerant quantum computing (FTQC): one of the largest remaining hurdles for practical quantum computing, but also the gateway to scalable, reliable, real‑world quantum advantage.

Examples are the presented solutions are available as part of the open-source MQT toolkit: https://mqt.readthedocs.io/

BIO:

For more than 15 years, Prof. Robert Wille is working on topics in the domain of quantum computing and successfully established design automation concepts in this domain. The impact of his work is reflected by numerous awards such as Best Paper Awards, e.g., at TCAD and ICCAD, a DAC Under-40 Innovator Award, a Google Research Award, etc., collaborations with numerous industrial partners in this domain, as well as his involvement in prestigious projects and initiatives, e.g., within the scheme of an ERC Consolidator Grant or the comprehensive quantum computing initiative of the Munich Quantum Valley. He published more than 400 papers and served in editorial boards as well as program committees of numerous journals/conferences.

ABSTRACT:

The always increasing integration level of very complex CMOS- and emerging technology-based circuits in heterogenous architectures requires a holistic approach to properly address all quality and reliability issues. In more detail, state-of-the-art architectures developed for implementing high performance applications are being implemented using not only CMOS technology, but also emerging technologies, such as memristive devices. Memristive devices can assume at least two different resistive states, being able to implement not only memory elements, but also computing elements. Different types of memristive devices, classified according to their switching mode, conductive path and working mechanism. In this context, Resistive Random-Access Memories (RRAMs) represent one of the most promising candidates to complement and/or replace CMOS technology. These emerging memories address issues related to traditional memories’ manufacturing process, reliability, power consumption and performance. Despite these advantages, RRAMs are also susceptible to manufacturing deviations affecting their quality at time zero as well as to time-dependent deviations, which compromise their reliability during lifetime. In addition, the integration of these emerging memories with CMOS-based circuits poses significant design challenges. Thus, a holistic approach able to properly address these challenges, from design to obsolescence, is considered mandatory. Thus, the goal of this talk is to present the idea behind the lifecycle management approach assuming CMOS- and emerging technology-based architectures. A discussion about the main sources of quality and reliability issues according to the lifecycle phases as well as the possible solutions able to address these main issues will be presented. Finally, this talk will allow attendees to understand the lifecycle management choices available to ensure high-quality and -reliable state-of-the-art architectures based on CMOS and emerging technologies.

BIO:

Leticia Maria Bolzani Pöhls graduated in Computer Science and holds a master’s degree in Electrical Engineering. In 2008 she obtained her Ph.D. in Computer Engineering from Politecnico di Torino (Italy), was Professor at the School of Technology at PUCRS (Brazil) from 2021 to 2022 and in 2022 created and until 2024 led the Group of Test and Reliability of Emerging Applications at IDS at RWTH Aachen University (Germany). Since 2025 she leads the Group of Neuromorphic Hardware in the Department of System Architectures at IHP – Leibniz Institute for High Performance Microelectronics (Germany). She works as a member of IEEE Latin American Test Symposium’s (LATS) Steering Committee and the working group of VLSI-SoC. She participates in organizing committees of conferences such as ETS, DATE, DDECS, VTS, or ITC and received the 2021 JETTA-TTTC Best Paper Award, the IEEE LATS2022 Best Paper Award, and the HiPEAC 2023 Paper Award for her paper at the Design Automation Conference (DAC2023).

ABSTRACT:

The increasing complexity of digital systems challenges the scalability of traditional EDA methodologies. This keynote reflects on lessons learned from building industrial-grade processor IP and design automation tools, with a focus on architectural decisions, tool limitations, and key technical challenges encountered along the way. It then outlines emerging research directions in EDA, including higher abstraction levels, architecture–tool co-design, scalable verification, and AI-assisted design flows. Finally, it discusses how closer collaboration between academia and industry can help bring advanced research into commercial practice.

BIO:

Karel Masařík is a Founder and Chief Innovation Officer of Codasip and Director of the Czech Semiconductor Centre, one of the European semiconductor competence centres established under Pillar I of the EU Chips Act.

Karel received his Ph.D. in Computer Science from Brno University of Technology, where he led the development of key processor design technologies within a university technology incubator before founding Codasip in 2014. Under his leadership, Codasip became one of the early commercial pioneers of the RISC-V ecosystem, delivering processor EDA and IP products adopted across automotive, industrial, security, and high-performance computing domains.

As CEO, Karel led Codasip through multiple international funding rounds and global expansion. He later transitioned to the role of Chief Innovation Officer, focusing on long-term technology strategy and the development of advanced programs in processor architectures, functional safety, security, high-performance computing, and AI-enabled systems, while continuing to promote the adoption of the open RISC-V standard.

Since 2025, Karel has also served as Director of the Czech Semiconductor Centre, where he focuses on strengthening collaboration between academia, industry, and government, accelerating talent development, and translating advanced research into industrial capabilities. In this role, he actively contributes to aligning the Czech and European semiconductor ecosystem with broader EU strategic objectives, bridging research excellence with sustainable industrial impact.